Design and Simulation of Output Queuing with the Middle Stage Buffered (OQMB) Clos Packet Switching Network

Clos network, a family of multistage networks, are attractive alternative for constructing scalable packet switches because of its distributed and modular design. The clos packet switching networks are the next step in scaling current crossbar switches to large number of ports. This paper presents the design and simulation of buffer lessbuffered-buffered Clos Packet switching network architecture. This paper proposes a novel the output queuing with the middle stage buffered (OQMB) Clos Packet switching architecture that does not need any schedulers. This architecture employs an ID matching with OQMB packet switching and desynchronize static round robin (DSRR) scheme to achieve Maximum throughput under any admissible traffic. Our queuing analysis demonstrates that only small size buffers are needed in the central stage. The only trade off for the proposed (OQMB) architecture is to employ small extra resequencing buffers. Input modules with desynchronize static round robin (DSRR) scheme connection scheme guarantees no cell contention in input stages. As a result, the OQMB architecture can achieve very high performance, and high throughput under any admissible traffic.